Transmit driver architecture with a jtag configuration mode, extended equalization range, and multiple power supply domains
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United States of America Patent
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Nov 21, 2023
Grant Date -
May 18, 2023
app pub date -
Nov 16, 2021
filing date -
Nov 16, 2021
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Abstract
A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.
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