Duty adjustment circuit, and delay locked loop circuit and semiconductor memory device including the same
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United States of America Patent
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Oct 24, 2023
Grant Date -
Oct 6, 2022
app pub date -
Jun 17, 2022
filing date -
Aug 14, 2020
priority date (Note) -
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Abstract
A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.
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