Phase-locked loop (PLL) with direct feedforward circuit
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United States of America Patent
Stats
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Oct 3, 2023
Grant Date -
Nov 10, 2022
app pub date -
Jul 15, 2022
filing date -
Dec 13, 2018
priority date (Note) -
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status (Latency Note)
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Abstract
A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
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International Classification(s)
- 2022 Application Filing Year
- H03L Class
- 440 Applications Filed
- 300 Patents Issued To-Date
- 68.19 % Issued To-Date
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- H03L Class
- 0 % this patent is cited more than
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