Systems and methods for obfuscating a circuit design

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United States of America Patent

PATENT NO 11775722
SERIAL NO

17493576

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Abstract

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Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.

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Patent Owner(s)

Patent OwnerAddress
EFABLESS CORPORATIONSAN JOSE CA

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bell, Risto San Jose, US 10 62
Edwards, Robert Timothy Poolesville, US 10 74
Eid, Sherif Sunnyvale, US 12 95
Hughes, John M Hartford, US 63 2340
Irissou, Bertrand San Jose, US 11 65
Kassem, Mohamed K Carlsbad, US 11 64
Lanza, Lucio Palo Alto, US 10 78
Shaurette, Greg P Tahoe City, US 9 61
Srivastava, Rajeev Austin, US 14 111
Wishart, Michael S Hillsborough, US 11 64

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