Semiconductor device for reducing concentration of thermal stress acting on bonding layers
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United States of America Patent
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Sep 26, 2023
Grant Date -
Mar 4, 2021
app pub date -
Jul 27, 2020
filing date -
Aug 27, 2019
priority date (Note) -
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status (Latency Note)
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Abstract
There is provided a semiconductor device that includes a wiring layer, a plurality of bonding layers arranged on the wiring layer and having conductivity, and a semiconductor element having a rear surface facing the wiring layer and a plurality of pads provided on the rear surface, and bonded to the wiring layer via the plurality of bonding layers, wherein the plurality of bonding layers are arranged in a grid shape when viewed along a thickness direction, wherein each of the plurality of pads is electrically connected to a circuit formed inside the semiconductor element and any of the plurality of bonding layers, and wherein at least one of the plurality of pads is located to be spaced apart from the plurality of bonding layers when viewed along the thickness direction.
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