Method of forming multiple-Vt FETS for CMOS circuit applications
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United States of America Patent
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Sep 5, 2023
Grant Date -
Dec 2, 2021
app pub date -
Aug 6, 2021
filing date -
Nov 16, 2017
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Abstract
A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.
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