Synchronized parallel tile computation for large area lithography simulation
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United States of America Patent
Stats
-
Sep 5, 2023
Grant Date -
Sep 15, 2022
app pub date -
May 23, 2022
filing date -
Nov 15, 2017
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
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International Classification(s)
- 2022 Application Filing Year
- G21K Class
- 150 Applications Filed
- 46 Patents Issued To-Date
- 30.67 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- G21K Class
- 0 % this patent is cited more than
- 2 Age
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