Scalable 2.5D interface circuitry

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United States of America Patent

PATENT NO 11741042
SERIAL NO

17561917

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

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Patent Owner(s)

Patent OwnerAddress
ALTERA CORPORATIONSAN JOSE CA

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rahman, Arifur San Jose, US 106 3243
Teh, Chee Hak Bayan Lepas, MY 82 546

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges56972148251393526311101 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 700250050007500100001250015000175002000022500250002750030000325003500037500400004250045000475005000052500550005750060000

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