Shape memory storage for electrical circuit autorouting
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United States of America Patent
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Aug 1, 2023
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N/A
app pub date -
Aug 18, 2021
filing date -
Aug 18, 2020
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Abstract
A method to store the shapes of an electrical circuit design in a hierarchical set of arrays that inverts the layout size order by area includes defining a plurality of storage levels. Each level corresponds to a two-dimensional projection of the three-dimensional volume of the circuit layout. Accordingly, each level subsumes the entire physical space of the circuit layout. Each level may include a respective grid of slots. The slots may be rectangular. Each slot within any single level may be the same size and dimensions as every other slot in this level. Shapes are added to this storage technique based upon size, not based upon physical layer. Each slot can contain shapes from any physical layer as long as that shape fits entirely within the slot.
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