Evaluation apparatus for semiconductor device

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United States of America Patent

PATENT NO 11709199
APP PUB NO 20210025936A1
SERIAL NO

16967280

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Abstract

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As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.

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Patent Owner(s)

Patent OwnerAddress
HITACHI HIGH-TECH CORPORATION17-1 TORANOMON 1-CHOME MINATO-KU TOKYO 105-6409

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujimura, Toru Tokyo, JP 20 95
Hirano, Ryo Tokyo, JP 51 188
Kageyama, Akira Tokyo, JP 41 355
Kato, Shigehiko Tokyo, JP 4 2
Komori, Masaaki Tokyo, JP 19 166
Mizuno, Takayuki Tokyo, JP 84 596
Nara, Yasuhiko Tokyo, JP 51 566
Ohki, Katsuo Tokyo, JP 6 74
Ohtaki, Tomohisa Tokyo, JP 23 174

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