Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices

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United States of America Patent

PATENT NO 11705432
APP PUB NO 20210327856A1
SERIAL NO

17365741

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Abstract

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Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INCIDAHO IDAHO

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bansal, Raj K Taichung, TW 24 13
Fujisawa, Hiroki Tokyo, JP 176 2626
Isa, Satoshi Tokyo, JP 55 436
Katagiri, Mitsuaki Tokyo, JP 79 1055
Kuwahara, Shunji Tokyo, JP 7 60

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