Passive sample-and-hold analog-to-digital converter with split reference voltage
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United States of America Patent
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Jul 11, 2023
Grant Date -
May 4, 2023
app pub date -
Oct 29, 2021
filing date -
Oct 29, 2021
priority date (Note) -
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Abstract
An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.
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