Distortion reduction circuit
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United States of America Patent
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Jul 4, 2023
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N/A
app pub date -
Nov 23, 2021
filing date -
Nov 23, 2021
priority date (Note) -
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Abstract
An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.
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