Memory component with a bus to transmit data for a machine learning operation and another bus to transmit host data
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United States of America Patent
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Jun 20, 2023
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N/A
app pub date -
Oct 14, 2019
filing date -
Oct 14, 2019
priority date (Note) -
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Abstract
Memory cells can include a memory region to store a machine learning model and input data and another memory region to store host data from a host system. An in-memory logic can be coupled to the plurality of memory cells and can perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and can provide the additional host data to the memory component for the other memory region of the plurality of memory cells. An additional bus can receive machine learning data from the host system and can provide the machine learning data to the memory component for the in-memory logic that is to perform the machine learning operation.
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