Offset calibration for successive approximation register analog to digital converter
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United States of America Patent
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Jun 6, 2023
Grant Date -
Oct 6, 2022
app pub date -
Apr 25, 2022
filing date -
Aug 3, 2018
priority date (Note) -
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status (Latency Note)
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Abstract
Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.
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