Low power digital-to-time converter (DTC) linearization
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United States of America Patent
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Apr 18, 2023
Grant Date -
Dec 8, 2022
app pub date -
Jun 7, 2021
filing date -
Jun 7, 2021
priority date (Note) -
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Abstract
An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.
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