Multiplexor for a semiconductor device
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United States of America Patent
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Feb 21, 2023
Grant Date -
Sep 8, 2022
app pub date -
Mar 3, 2021
filing date -
Mar 3, 2021
priority date (Note) -
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Abstract
A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.
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