Control system with delayed protection for a three-level inverter
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United States of America Patent
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Jan 31, 2023
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N/A
app pub date -
Jun 7, 2021
filing date -
Jun 8, 2020
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Abstract
A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.
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