Phase-locked loop with dual input reference and dynamic bandwidth control
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United States of America Patent
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Jan 17, 2023
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N/A
app pub date -
Nov 29, 2021
filing date -
Dec 16, 2020
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Abstract
Disclosed herein are systems and methods for improved performance of phase-locked loop based clock generators, particularly in the context of wireless audio. A PLL clock generator includes a PLL core configured to receive a module reference clock provided by a communications module and generate a subsystem data clock corresponding to a module data clock of the communications module; and a data clock tracker module configured to receive the module data and subsystem data clocks and determine a corresponding data clock correction factor. The bandwidth of the PLL core may be dynamically changed thereby enabling both fast and very precise settling. The PLL core may use a low jitter frequency reference for the phase detector while an a synchronous and jitter-prone audio sample clock is used to ensure a mean frequency of the PLL core tracks the audio sample clock.
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