Memory system and operating method thereof
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United States of America Patent
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Dec 27, 2022
Grant Date -
Dec 3, 2020
app pub date -
Nov 12, 2019
filing date -
May 29, 2019
priority date (Note) -
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Abstract
A memory system includes: a memory device; a command queue queuing a program descriptor and a first read descriptor, and sequentially outputting the descriptors; a program manager performing an error handling operation in response to the program descriptor, the error handling operation including performing a program operation on a second physical address when a program operation performed on a first physical address fails; a fail managing buffer storing the first physical address for the failed program operation; a queue manager deleting the first read descriptor from the command queue and outputting an exception signal, when a physical address of the first read descriptor is the same as the first physical address; and a descriptor generator generating a second read descriptor including the second physical address in response to the exception signal and enqueuing the second read descriptor in the command queue, when the error handling operation passed.
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