Method of forming interconnect for semiconductor device
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United States of America Patent
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Nov 22, 2022
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N/A
app pub date -
Oct 24, 2019
filing date -
Oct 24, 2019
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Abstract
A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.
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