Clock drive circuit

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United States of America Patent

PATENT NO 11502657
APP PUB NO 20210135641A1
SERIAL NO

17040516

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Abstract

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A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

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Patent Owner(s)

Patent OwnerAddress
NO 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONCHONGQING

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Guangbing Chongqing, CN 52 56
Chen, Xi Chongqing, CN 903 6756
Fu, Dongbing Chongqing, CN 45 23
Huang, Xingfa Chongqing, CN 7 6
Li, Liang Chongqing, CN 515 3124
Shen, Xiaofeng Chongqing, CN 27 44
Wang, Jian'an Chongqing, CN 26 11
Xu, Mingyuan Chongqing, CN 16 27

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