Interconnection network with adaptable router lines for chiplet-based manycore architecture
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United States of America Patent
Stats
-
Nov 1, 2022
Grant Date -
Nov 4, 2021
app pub date -
Oct 30, 2020
filing date -
May 4, 2020
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.
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Patent Citation Ranking
- 1 Citation Count
- H04L Class
- 62.65 % this patent is cited more than
- 3 Age
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