Method of forming multi-threshold voltage devices and devices so formed
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United States of America Patent
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Oct 18, 2022
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N/A
app pub date -
Aug 26, 2019
filing date -
Oct 20, 2017
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Abstract
A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.
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