Read assist circuitry for memory applications
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United States of America Patent
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Oct 18, 2022
Grant Date -
Mar 18, 2021
app pub date -
Nov 30, 2020
filing date -
Aug 30, 2017
priority date (Note) -
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status (Latency Note)
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Abstract
Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.
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