Methods for polishing dielectric layer in forming semiconductor device
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United States of America Patent
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Oct 4, 2022
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N/A
app pub date -
Jan 29, 2021
filing date -
Dec 23, 2020
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Abstract
Methods for polishing dielectric layers using an auto-stop slurry in forming semiconductor devices, such as three-dimensional (3D) memory devices, are provided. For example, a stack structure is formed in a staircase region and a core array region. The stack structure includes a plurality of interleaved first material layers and second material layers. Edges of the interleaved first material layers and second material layers define a staircase structure on a side of the stack structure in the staircase region. A dielectric layer is formed over the staircase region and a peripheral region outside the stack structure. The dielectric layer includes a protrusion from the stack structure. The dielectric layer is polished using an auto-stop slurry to remove the protrusion of the dielectric layer.
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