Demultiplexing circuit, multiplexing circuit, and channelizer relay unit
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United States of America Patent
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Sep 27, 2022
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N/A
app pub date -
Mar 5, 2018
filing date -
Mar 6, 2017
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Abstract
A multi-stage demultiplexing circuit in which a plurality of circuits each combining a selector and a frequency decimation circuit are connected is included. The selector selects one of input signals based on a control signal, and generates a plurality of output signals. The plurality of output signals output from the selector are input to the frequency decimation circuit, and the frequency decimation circuit performs frequency conversion processing, low pass filter processing, and down-sampling processing based on a control signal to generate an output signal. Two or more reception signals are input to the multi-stage demultiplexing circuit, and the multi-stage demultiplexing circuit executes demultiplexing processing based on a control signal so that an output signal that includes an unused band portion is prevented from being output downstream.
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