Phase-locked loop circuit having linear voltage-domain time-to-digital converter with output subrange
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United States of America Patent
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Sep 27, 2022
Grant Date -
May 12, 2022
app pub date -
Sep 29, 2021
filing date -
Nov 12, 2020
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Abstract
A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
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