Systems and methods for monitoring and responding to bus bit error ratio events
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United States of America Patent
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Aug 23, 2022
Grant Date -
Feb 4, 2021
app pub date -
Aug 2, 2019
filing date -
Aug 2, 2019
priority date (Note) -
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Abstract
A computer system includes a bus interface having error correction capability. The bus interface includes an error register that is configured to provide error information related to correctable errors. System software within the computer system is configured to obtain the error information from the error register and calculate a bit error metric based on the error information. A baseboard management controller within the computer system is configured to take an action in response to obtaining the bit error metric from the system software and determining that a condition related to the bit error metric has been satisfied.
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