Programmable frequency DLL
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United States of America Patent
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Aug 2, 2022
Grant Date -
Aug 12, 2021
app pub date -
Feb 15, 2021
filing date -
Feb 11, 2020
priority date (Note) -
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status (Latency Note)
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Abstract
A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.
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