Digital return receiver with digital data aggregation
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United States of America Patent
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Jun 14, 2022
Grant Date -
May 27, 2021
app pub date -
Nov 25, 2020
filing date -
Nov 26, 2019
priority date (Note) -
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Abstract
In some embodiments, a digital clock management system includes input signal conversion circuitry, logic circuitry and output signal conversion circuitry. The input signal conversion circuitry converts input signals to corresponding first digital data streams, each of which contains digital data synchronized to a first data clock. First digital logic circuitry converts the first digital data streams to second digital data streams, each of which contains digital data synchronized to the first data clock, and converts the second digital data streams to third digital data streams, each of which contains digital data synchronized to a common clock. Second digital logic circuitry converts the third digital data streams to a single digital data stream. The output signal conversion circuitry converts the single digital data stream to a modulated output signal.
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