Clock and data recovery and associated signal processing method
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United States of America Patent
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May 31, 2022
Grant Date -
Jul 30, 2020
app pub date -
Jan 16, 2020
filing date -
Jan 28, 2019
priority date (Note) -
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Abstract
The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.
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