Memory device having error correction function and operating method thereof
Number of patents in Portfolio can not be more than 2000
United States of America
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May 10, 2022
Grant Date -
Oct 24, 2019
app pub date -
Apr 19, 2019
filing date -
Apr 19, 2019
priority date (Note) -
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Abstract
A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.
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