Dynamic partitioning of execution resources

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11307903
APP PUB NO 20190235928A1
SERIAL NO

15885751

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Abstract

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Embodiments of the present invention set forth techniques for allocating execution resources to groups of threads within a graphics processing unit. A compute work distributor included in the graphics processing unit receives an indication from a process that a first group of threads is to be launched. The compute work distributor determines that a first subcontext associated with the process has at least one processor credit. In some embodiments, CTAs may be launched even when there are no processor credits, if one of the TPCs that was already acquired has sufficient space. The compute work distributor identifies a first processor included in a plurality of processors that has a processing load that is less than or equal to the processor loads associated with all other processors included in the plurality of processors. The compute work distributor launches the first group of threads to execute on the first processor.

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Patent Owner(s)

Patent OwnerAddress
NVIDIA CORPORATION2788 SAN TOMAS EXPRESSWAY SANTA CLARA CA 95051

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Duluk,, Jr Jerome F Palo Alto, US 112 1145
Durant, Luke San Jose, US 16 148
Hirota, Gentaro San Jose, US 18 397
Menezes, Alan San Jose, US 9 12
Navarro, Ramon Matas Newburyport, US 4 5
Pharris, Brian Cary, US 9 27
Tuckey, Jeffrey Saratoga, US 2 4

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