Systems and methods for obfuscating a circuit design

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11301609
APP PUB NO 20200285795A1
SERIAL NO

16879045

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Abstract

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Systems and methods for managing operations for generating a plurality of designs of an integrated circuit chip are described. One of the methods includes receiving a request with a specification of the integrated circuit chip from a requester account, receiving a plurality of requests from a plurality of community member accounts for viewing the specification, and providing access to the specification to the plurality of community member accounts. The method further includes receiving a plurality of instances of the acceptance from the plurality of community member accounts for creating the plurality of designs, providing access to a plurality of resources to the plurality of community member accounts, and receiving a plurality of design files having the plurality of designs from the plurality of community member accounts. The method includes providing access to the plurality of designs to the requester account for approval or disapproval of the plurality of designs.

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Patent Owner(s)

Patent OwnerAddress
EFABLESS CORPORATIONSAN JOSE CA

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bell, Risto San Jose, US 10 62
Edwards, Robert Timothy Poolesville, US 10 74
Eid, Sherif Sunnyvale, US 12 95
Hughes, John M Hartford, US 63 2340
Irissou, Bertrand San Jose, US 11 65
Kassem, Mohamed K Carlsbad, US 11 64
Lanza, Lucio Palo Alto, US 10 78
Shaurette, Greg P Tahoe City, US 9 61
Srivastava, Rajeev Austin, US 14 111
Wishart, Michael S Hillsborough, US 11 64

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