Differential mixed signal multiplier with three capacitors
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United States of America
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Apr 12, 2022
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Oct 14, 2021
app pub date -
Apr 13, 2020
filing date -
Apr 13, 2020
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Abstract
A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
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