Co-integrated high voltage (HV) and medium voltage (MV) field effect transistors
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United States of America
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Mar 29, 2022
Grant Date -
Oct 21, 2021
app pub date -
Apr 15, 2020
filing date -
Apr 15, 2020
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Abstract
The present disclosure relates to semiconductor structures and, more particularly, to co-integrated high voltage and medium voltage devices and methods of manufacture. The structure includes a substrate having a semiconductor on insulator (SOI) region and a bulk region; and a first device formed on the bulk region, the first device having a first gate dielectric layer and a second gate dielectric layer surrounding the first dielectric layer, and a thickness of the first gate dielectric layer and the second gate dielectric layer being greater than a thickness of an insulator layer of the SOI region.
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