Dual-mode high-bandwidth SRAM with self-timed clock circuit
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United States of America
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Mar 8, 2022
Grant Date -
Jul 22, 2021
app pub date -
Apr 6, 2021
filing date -
Apr 6, 2021
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Abstract
A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.
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