CMOS varactor with increased tuning range
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United States of America
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Mar 1, 2022
Grant Date -
Nov 16, 2017
app pub date -
Dec 24, 2014
filing date -
Dec 24, 2014
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Abstract
A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.
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