Monolithic integration of enhancement mode and depletion mode field effect transistors

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 11264379
APP PUB NO 20200381425A1
SERIAL NO

16996162

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Abstract

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A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.

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Patent Owner(s)

Patent OwnerAddress
WIN SEMICONDUCTORS CORPTAOYUAN CITY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Chia-Ming Tao Yuan, TW 220 956
Chung, Jung-Tao Tao Yuan, TW 9 17
Lin, Yan-Cheng Tao Yuan, TW 8 5
Tseng, Lung-Yi Tao Yuan, TW 3 0

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