Transient stabilized SOI FETs

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11251140
APP PUB NO 20200350267A1
SERIAL NO

16875615

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Abstract

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Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

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Patent Owner(s)

Patent OwnerAddress
PSEMI CORPORATION9369 CARROLL PARK DRIVE SAN DIEGO CALIFORNIA 92121 92121

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bargroff, Keith San Diego, US 60 721
Englekirk, Robert Mark Littleton, US 96 1663
Murphy, Christopher C Lake Zurich, US 36 333
Ranta, Tero Tapio San Diego, US 114 1692
Willard, Simon Edward Irvine, US 76 711

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