Neural network unit that interrupts processing core upon condition
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United States of America
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Jan 11, 2022
Grant Date -
Sep 27, 2018
app pub date -
May 31, 2018
filing date -
May 31, 2018
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Abstract
A programmable apparatus includes a program memory that holds instructions of a program fetched and executed by the apparatus, a data memory that holds data processed by the instructions, a status register that holds a status having fields: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count that indicates a number of times an operation specified in a current program instruction remains to be performed. A condition register has condition fields corresponding to the status register fields. Control logic generates an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.
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