Semiconductor system capable of scrambling addresses
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United States of America
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Jan 4, 2022
Grant Date -
Aug 20, 2020
app pub date -
Nov 18, 2019
filing date -
Nov 18, 2019
priority date (Note) -
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Abstract
A semiconductor system in accordance with an embodiment includes a module controller and a plurality of semiconductor chips configured to receive logical addresses from the module controller. The semiconductor system also includes a plurality of scramble circuits, with a scramble circuit provided for each of the plurality of semiconductor chips, configured to receive the logical addresses and to output corresponding physical addresses for the plurality of semiconductor chips. Each scramble circuit of the plurality of scramble circuits is configured to receive the same logical address and to output a corresponding physical address different from the physical addresses output by the other scramble circuits of the plurality of scramble circuits.
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