Nonvolatile memory apparatus for mitigating read disturbance and system using the same

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United States of America Patent

PATENT NO 11145364
APP PUB NO 20200402576A1
SERIAL NO

16738945

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Abstract

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A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

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Patent Owner(s)

Patent OwnerAddress
SK HYNIX INCICHEON-SI

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheon, Jun Ho Seoul, KR 20 46
Kang, Seok Joon Seoul, KR 21 76
Park, Moo Hui Icheon-si, KR 5 4

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Patent Citation Ranking

  • 2 Citation Count
  • G11C Class
  • 48.00 % this patent is cited more than
  • 4 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges27972865903916214401 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 700200400600800100012001400160018002000220024002600280030003200

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