Signal calibration circuit
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United States of America Patent
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Sep 28, 2021
Grant Date -
N/A
app pub date -
Sep 14, 2020
filing date -
Sep 14, 2020
priority date (Note) -
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status (Latency Note)
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Abstract
This disclosure relates to a circuit comprising a first, second, and third data latch, and an input for a data signal. The first data latch may be configured to sample a delayed version of the data signal in response to a first control signal. The second data latch may be configured to sample the delayed version of the data signal in response to a run clock signal. The run clock signal may be configured to run for a predefined number of clock cycles subsequent to the first control signal. The third data latch may be configured to sample either an output signal of the first data latch or an output signal of the second data latch in response to a second control signal received after the predefined number of clock cycles of the run clock signal.
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