Systems and methods for writing zeros to a memory array
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United States of America Patent
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Sep 28, 2021
Grant Date -
Jan 21, 2021
app pub date -
Oct 5, 2020
filing date -
Dec 11, 2017
priority date (Note) -
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Abstract
A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.
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