Fabrication of transistors having stressed channels

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United States of America Patent

PATENT NO 11121043
APP PUB NO 20190244869A1
SERIAL NO

16230192

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Abstract

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There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

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Patent Owner(s)

Patent OwnerAddress
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES75015 PARIS

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Le, Royer Cyrille Tullins-Fures, FR 29 141
Morand, Yves Grenoble, FR 56 759
Posseme, Nicolas Sassenage, FR 98 414

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