Systems and methods for plate voltage regulation during memory array access
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United States of America Patent
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Aug 10, 2021
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N/A
app pub date -
Aug 30, 2019
filing date -
Dec 6, 2017
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Abstract
A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.
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