PVT compensated delay cell for a monostable
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United States of America Patent
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Jul 6, 2021
Grant Date -
Dec 31, 2020
app pub date -
Jun 27, 2019
filing date -
Jun 27, 2019
priority date (Note) -
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Abstract
A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.
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