Clock pulse generation circuit
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United States of America Patent
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Jun 15, 2021
Grant Date -
Dec 5, 2019
app pub date -
Aug 19, 2019
filing date -
May 4, 2018
priority date (Note) -
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Abstract
In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.
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